Program controlled data processing system

ABSTRACT

A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.

United States Patent [72] Inventors Randall W. Downing Wheaten, 111.; Michael P. Fsblseh. Bronx, N.Y.; John A. Herr, Geneva; John S. Novvult. Whecton: Frank F. Taylor. West Chicago; Werner Ulrich. Glen Ellyn. 111. [21 1 Appl. No. 685,642 [221 Filed Nov. 24. 1967 Dlvlsion of Application Ser. No. 334. 75. Dec. 31. 1963. [4S] Patented Mar. 2,1971 [73] Assignee Bell Telephone Laboratories Incorporated New York, N.\'.

(54] PROGRAM CONTROLLED DATA PROCESSING SYSTEM 31 Claims, 74 Drawing Figs.

{52] US. Cl. 340/1715 [51] laLCI. G06l9/18 {50] Fleldofsesrch 340/1725; 235/157 [56] References Cited UNITED STATES PATENTS 3,289,168 11/1966 Walton et a1. 340/1725 3,286,236 11/1966 Logan et a1. 340/1725 Primary Examiner-Gareth D. Show Attorneys-R. J. Guenther and James Warren Fallt ABSTRACT: A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs. which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.

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1. In combination: memory means containing a plurality of sequences of program order words and system data; said sequences including timed interrupt program sequences; said program order words including inhibit interrupt order words; a central control comprising; means for obtaining information from said memory means, means for writing information into said memory means and means responsive to said information obtained from said memory means for executing said sequences of program order words; clock means for generating signals defining machine cycles and times within said machine cycles and means responsive to said clock signals for generating timed interrupt signals; interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said program order words upon completion of the work functions of the order word being executed at the time said timed interrupt signal occurs; means for initiating said timed interrupt program sequence; and said central control further comprising means for delaying the response of said interrupt means to said timed interrupt signals when said order word being executed at the time of occurrence of said timed interrupt signal is said inhibit interrupt program order word.
 2. In combination: memory means containing sequences of program order words and data, said sequences including; (a) a base level program sequence, (b) timed interrupt program sequences, and (c) maintenance interrupt program sequences, a central control comprising; means for reading information from said memory means and for writing data into said memory means, means for executing said program sequences, means for initiating the execution of said base level program sequences; clock means defining machine cycles and times within said machine cycles; interrupt timing means responsive to said clock signals for generating cyclically recurring timed interrupt signals; timed interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said base level program sequences and for initiating said timed interrupt program sequences; a plurality of operational checking means for checking the execution of said base level program sequences and said timed interrupt program sequences and for generating a trouble signal upon detection of trouble in said execution; and maintenance interrupt means responsive to said trouble signals for halting the execution of said timed interrupt program sequences and said base level program sequences and for initiating execution of said maintenance interrupt program sequences.
 3. The combination in accordance with claim 2 wherein: said maintenance interrupt program sequences comprise a plurality of program sequences discrete to said operational checking means; said maintenance interrupt means comprises a plurality of maintenance interrupt sources discrete to associated ones of said maintenance interrupt program sequences and to associated ones of said operational checking means, said operational checking means check the execution of said maintenance interrupt program sequences and generate trouble signals upon detection of trouble in execution thereof; and certain of said maintenance interrupt sources being responsive to trouble signals of their associated operational checking means to halt the execution of certain of said maintenance interrupt program sequences and to initiate execution of said maintenance interrupt program sequences associated with said certain maintenance interrupt sources.
 4. In combination: a memory system containing sequences of program order words and system data; a central control comprising means for reading information from said memory and for executing said sequences, said system data includes an ordered list of classes of base level jobs to be performed; said list defining a Base level executive program and comprising a plurality of sublevel entries with identical sublevel entries for each time a class of job is to be performed in the execution of said base level executive program; and said program sequences including sequences for executing said base level executive program.
 5. The combination in accordance with claim 4 wherein: said system data includes a plurality of job request registers uniquely associated with said classes of jobs; said sequences of program order words include a plurality of sublevel job supervisory program sequences uniquely associated with said classes of jobs and a plurality of job program sequences; said central control comprises means for entering job requests in said job request registers; means responsive to said sublevel job supervisory program sequences for examining said job request registers to detect job requests and to generate job request signals; and means responsive to said job request signals to initiate execution of a selected one of said job program sequences.
 6. In combination: a memory system containing sequences of program order words and system data; said memory system including a plurality of job request registers, certain of said job request registers being interject registers a central control comprising means for reading information from said memory system and for executing said sequences of program order words; said sequences of program order words including base level program sequences and timed interrupt program sequences; said base level program sequences including interject program sequences; means for reading information from said memory system and for writing data into said memory system; means for executing said program sequences; means for initiating the execution of said base level program sequences; clock means defining machine cycles and times within said machine cycles; interrupt timing means responsive to said clock signals for generating timed interrupt signals; timed interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said base level program sequences and for initiating said timed interrupt program sequences; said timed interrupt program sequences including interject request recording program sequences; said central control responsive to the execution of said interject request program sequences for entering interject requests in said interject request registers; said central control responsive to the execution of said base level program sequences for examining said interject request registers to generate interject request signals upon detection of an interject request; and said central control responsive to said interject request signals during the execution of said base level program sequences to initiate said interject program sequences.
 7. In combination: memory means containing sequences of program order words and system data, said memory means comprising a plurality of interrupt registers; said sequences including a base level program sequence and interrupt program sequences, a central control comprising reading means for reading information from said memory means; writing means for writing data into said memory means, a plurality of flip-flop registers, means for executing said program sequences; means for initiating the execution of said base level program sequence; a plurality of interrupt sources for generating interrupt signals; means responsive to said interrupt signals for interrupting the execution of said base level program sequences, for enabling said writing means to write into said interrupt registers the contents of a first plurality of said flip-flop registers, to reset a second plurality of said flip-flop registers and to selectively initiate the execution of said interrupt program sequences; said interrupt program sequences including a go back to normal pRogram order word, and said central control comprises means responsive to the execution of the said go back to normal order word for enabling said reading means to read from said data store the contents of said interrupt registers; means for inserting in said first plurality of flip-flop registers the contents of said interrupt registers; and means for initiating said base level program sequence to first execute the order word in the sequence following the order word which was being executed at the time said interrupt signal occurred.
 8. The combination in accordance with claim 7 wherein said means for executing said program sequences comprises decoding means responsive to said program order words, and said means responsive to the execution of said go back to normal order word comprises a go back to normal sequencer which generates signals for momentarily inhibiting the operation of said decoding means and enabling said reading means.
 9. In combination: memory means containing sequences of program order words and system data; said sequences including a base level program sequence and a plurality of interrupt program sequences; said memory means comprises a plurality of interrupt registers discrete to said interrupt program sequences; a central control comprising: reading means for reading information from said memory means; writing means for writing data into said memory means; means for executing said program sequences; means for initiating the execution of said base level program sequences; a plurality of flip-flop registers; a plurality of interrupt sources for generating a plurality of discrete interrupt signals unique to said interrupt program sequences; means for selectively enabling said interrupt sources; and means responsive to said discrete interrupt signals for enabling said writing means to place the contents of certain of said flip-flop registers in the interrupt register discrete to the enabled interrupt source and to initiate the interrupt program sequence discrete to the enabled interrupt source.
 10. In combination: memory means containing sequences of program order words and system data; said sequences including a base level program sequence and an interrupt program sequence; said base level program sequences including interrupt sensitive program sequences; a central control comprising means for reading information from said store and for writing data into said data store; means for executing said program sequences; means for initiating the execution of said base level program sequences; an interrupt occurred flip-flop; means for generating interrupt signals; means responsive to said interrupt signals to set said interrupt occurred flip-flop to a first state, to momentarily halt the execution of said base level program sequences and to initiate said interrupt program sequences; means responsive to the execution of said interrupt program sequences for halting the execution of said interrupt program sequences and for reinitiating the execution of said base level program sequences; means responsive to the execution of said interrupt sensitive program sequences including means for examining the state of said interrupt occurred flip-flop; and means responsive to the state of said interrupt occurred flip-flop for modifying the execution of said interrupt sensitive program sequences.
 11. In combination: memory means containing sequences of program order words and data; said sequences including base level program sequences; interrupt program sequences and test interrupt program sequences; said base level program sequences including maintenance program sequences; a central control comprising means for reading information from said memory means and for writing data into said memory means; means for executing said program sequences; means for initiating the execution of said base level program sequencEs; means for generating interrupt request signals; a test interrupt flip-flop; means responsive to the execution of said maintenance program sequences to set said test interrupt flip-flop to a first state; and means responsive to said interrupt request signals and to an output signal of said test interrupt flip-flop to initiate the execution of said test interrupt program sequence and to reset said test interrupt flip-flop.
 12. In combination: a program store containing a plurality of sequences of program order words; said sequences including base level program sequences and interrupt program sequences; a data store containing system data; a central control comprising means for reading information from said stores and for writing data into said data store; means for executing said program sequences; means for initiating the execution of said base level program sequences; means for generating interrupt signals; and means responsive to said interrupt signals for momentarily halting the execution of said base level program sequences upon completion of the work functions of the order word being executed at the time said interrupt signal occurred and for initiating the execution of said interrupt program sequences.
 13. In combination: memory means containing sequences of program order words and data; said sequences including a base level program sequence and interrupt program sequences; said program sequences including reference point program sequences; a central control comprising means for reading information from said memory means and for writing data into said memory means; means for executing said program sequences; means for initiating the execution of said base level program sequence; means for generating interrupt signals; means responsive to said interrupt signals to momentarily halt the execution of said base level program sequences and to initiate said interrupt program sequences; operational checking means for observing the execution of said interrupt program sequences and for generating trouble signals upon detection of trouble in execution thereof; an interrupt trouble occurred register responsive to said trouble signals to set said register to a first state; means responsive to the execution of said interrupt program sequences for halting the execution of said interrupt program sequences; and means responsive to the halting of said interrupt program sequences and the state of said interrupt trouble occurred flip-flop to initiate the execution of said reference point program sequences.
 14. In combination: memory means containing information comprising sequences of program order words and system data; said sequences including call processing and maintenance program sequences and a plurality of interrupt program sequences; a central control; said central control comprising means for obtaining said information from said memory means; means for writing data into said memory means; means for executing said sequences of program order words; a plurality of interrupt sources uniquely associated with said interrupt program sequences; said interrupt sources being assigned a relative interrupt priority level in an ordered priority arrangement; a plurality of interrupt level activity flip-flops; means for selectively enabling said level activity flip-flops; means for selectively enabling said interrupt sources; and interrupt sequencer means responsive to output signals of said interrupt sources and of said level activity flip-flops to initiate execution of the interrupt program sequence associated with the enabled interrupt source having the highest relative level of priority.
 15. The combination in accordance with claim 14 wherein a plurality of said interrupt sources are assigned the same relative level of priority; wherein said interrupt program sequences comprise interrupt level pRogram sequences and interrupt source program sequences; and wherein said interrupt sequencer initiates execution of the interrupt level program sequence associated with the enabled interrupt source having the highest relative priority to record in said memory means the contents of a portion of said central control and to examine the states of said plurality of interrupt sources associated with said interrupt level program sequence to generate an output signal defining an interrupt source program sequence associated with an enabled one of said plurality of interrupt sources; and further comprising means responsive to said output signal for initiating execution of the interrupt source program sequence associated with said enabled interrupt source.
 16. In combination: a central processor comprising a program store containing information comprising sequences of program order words and system data; said sequences including call processing and maintenance program sequences and a plurality of interrupt program sequences; a data store containing information comprising additional system data; a central control; said central control comprising means for obtaining said information from said stores; means for writing data into said data store; a go back to normal sequence circuit; means for executing said sequences of program order words; a plurality of interrupt sources uniquely associated with said interrupt program sequences; said interrupt sources being assigned a relative interrupt priority level in an ordered priority arrangement; a plurality of interrupt level activity flip-flops; means for selectively enabling said level activity flip-flops; means for selectively enabling said interrupt sources; interrupt sequencer means responsive to output signals of said interrupt sources and of said level activity flip-flops to initiate the execution of the interrupt program sequence associated with the enabled interrupt source having the highest relative level of priority; means responsive to the execution of said initiated interrupt program sequence to reset the interrupt source associated with said sequence being executed; said initiated interrupt program sequence including a go back to normal order word; and means responsive to said go back to normal order word for enabling said go back to normal sequence circuit to reset said level activity flip-flop associated with the initiated interrupt program sequence.
 17. A central processor for a program controlled electrical control system comprising: a program store containing sequences of program order words for controlling the operation of said control system; a data store containing data relating to the operation of said system and ordered pairs of words defining maintenance program sequences; a central control; means in said central control for reading program orders from said program store; means in said central control for generating code-addresses for reading said ordered pairs of words; and means responsive to said ordered pairs of words for controlling said control system.
 18. A program controlled data processing system comprising: a central data processor comprising a program store containing sequences of program order words and data; a data store for storing a plurality of words of data and pairs of words comprising maintenance program sequences; a central control; said central control comprising means responsive to said program order words for controlling said data processing and for reading information from said stores and for writing information into data store; said central control further comprising operational checking means to detect incorrect responses of said central data processor; and said central control responsive to output signals of said operational checking means to initiate execution of said data store maintenance program sequences.
 19. In combination: a program store containing information comprising sequences of program order words and system data; a data store containing information comprising additional system data and ordered pairs of words defining maintenance program sequences; a central control comprising means for obtaining said information from said stores; means for writing data into said data store; means for executing said sequences of program order words; sequencer means for obtaining from said data store said ordered pairs of words; operational checking means for generating a trouble signal upon detection of trouble in obtaining a particular ordered pair of words; and said sequencer means responsive to said trouble signals for rereading said data store to reobtain said particular ordered pair of words.
 20. The combination in accordance with claim 19 wherein said operational checking means is responsive to the rereading of said data store to check the obtaining of said data words and to generate a fault signal upon detection of trouble in obtaining information by said rereading.
 21. In combination: a program store containing sequences of program order words and data; a data store; a central control comprising means for reading information from each of said stores; decoding means responsive to program order words read from said program store for controlling said central control; checking means in said central control responsive to information read from said program store for checking the plausibility of said information; said checking means effective to generate an error signal upon detection of an implausible response; and means responsive to said error signals for momentarily interrupting the operation of said central control and for generating a program store command for rereading said program store at the address from which said implausible information was obtained.
 22. The combination in accordance with claim 21 wherein: said means responsive to said error signals comprises; a program store reread sequence circuit; and said program store reread sequence circuit effective to inhibit said decoding means and to control portions of said central control in effecting said rereading.
 23. In combination: a program store containing sequences of program order words and data, a data store for storing a plurality of words of data and a central control; said central control comprising means responsive to said program order words for reading information from said stores and for writing information into said data store; a plurality of operational checking means to detect incorrect responses of said central data processor and to generate a trouble signal upon detection of an incorrect response; means discrete to each of said operational checking means for recording the occurrence of said trouble signals; remedial means discretely enabled in response to said trouble signals for carrying out particular remedial actions, and a plurality of error counting registers discrete to each of said trouble signals; and each of said remedial means including means for incrementing said error counting register by a count of 1 each time said remedial means is enabled.
 24. In combination: a program store containing sequences of program order words and data, a data store containing system data and a central control; said central control comprising means for generating commands for reading information from said stores; means for executing said program orders obtained from said program stores; operational checking means for checking the validity of responses obtained from said program store and for generating trouble signals upon detection of an invalid response; and remedial means responsive to said trouble signal to obtain information to replace said invalid response.
 25. The combination in accordance with claim 24 wherein said operational checking means is responsive to said informAtion obtained by said remedial means to check the validity of said data and to generate a fault signal upon detection of invalid data.
 26. The combination in accordance with claim 25 wherein said central control comprises: means for recording the code-address of the location in said program store from which said invalid response was obtained; a flip-flop discrete to said fault signal for recording the occurrence of said fault signal; and means responsive to said fault signal for initiating further remedial work functions.
 27. In combination: a program store containing sequences of program order words, certain of said order words being single cycle order words and others of said order words being multicycle order words; a data store containing system data; a central control comprising means for reading information from said stores and for writing information into said data store; decoding means responsive to information read from said program store for generating output signals for controlling said central control; said output signals including a plurality of unique sequencer enable signals; clock means defining a central control machine cycle and a plurality of times within said cycle; said central control responsive to output signals of said decoding means to execute said single cycle orders at the rate of one single cycle order per machine cycle and to execute said multicycle orders at a rate less than one order per machine cycle; said central control further comprising multicycle sequencer means responsive to said sequencer enable signals for inhibiting output signals of said decoding means and for carrying out specified central control work functions defined by said unique sequencer enable signals; a plurality of operational checking means for checking the responses of said central processor during the enablement of said multicycle sequencer means and for generating a trouble signal upon detection of an improper central processor response; and means responsive to said trouble signals for momentarily inhibiting the action of said multicycle sequencer means and for carrying out remedial system work functions.
 28. In combination: a program store containing sequences of program order words; a data store containing system data; a central control; said central control comprising means for obtaining information from said program store and from said data store and for writing information in said data store; said central control comprising means for obtaining information from said stores and for executing said sequences of program order words; said central control concurrently operative with respect to a plurality of order words of said sequences; a plurality of operational checking means for checking the execution of each of said program order words and for generating a trouble signal discrete to said operational checking means upon detection of trouble in said execution; a plurality of remedial means; each of said remedial means associated with one of said operational check means; said remedial means enabled by trouble signals of said associated operational check means; output signals of certain of said recording means comprising inhibit signals to certain other remedial means not associated with said recording means to momentarily inhibit the operation of said nonassociated remedial means.
 29. In combination: a program store containing sequences of program order words; a data store; a central control comprising means for reading information from each of said stores; decoding means responsive to program order words read from said program store for controlling said central control; operational checking means responsive to information read from said data store for checking the plausibility of said information; said checking means generating a trouble signal upon detection of implausible information; and means reSponsive to said trouble signal for momentarily interrupting the operation of said central control and for generating a data store reread command for rereading said data store at the address from which said implausible information was obtained to obtain reread data.
 30. he combination in accordance with claim 29 wherein said operational checking means is responsive to said reread data to check the validity of said data and to generate a fault signal upon detection of implausible data.
 31. The combination in accordance with claim 30 wherein said central control comprises: means for recording the code-address of the location in said data store from which said implausible information was obtained; a flip-flop discrete to said fault signal for recording the occurrence of said fault signal; and means responsive to said fault signal for initiating other remedial work functions. 